1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for transferring data. Still more particularly, the present invention relates to a method and apparatus for transferring data from a memory subsystem to a network adapter.
2. Description of Related Art
The data processing systems include a bus architecture for transferring data between various components. One type of bus architecture is a Peripheral Component Interconnect (PCI). PCI provides a high-speed data path between the CPU and peripheral devices, such as memory subsystem, a network adapter, and a video adapter.
With respect to transferring data between a memory subsystem and an input/output (I/O) subsystem using a PCI bus, efficiencies in transferring data are dependent on cache aligned data transfers from the memory subsystem to the I/O subsystem. Efficiencies are greatest when the total data transfer is an integral multiple of the cache line size (CLS). For example, transfers to a disk storage system fit this model in which typical transfers have sizes, such as 512, 1024, 2048, and 4096 bytes.
These efficiencies are typically not found with some I/O subsystems, such as network adapters. For example, a maximum Ethernet frame size is 1514 bytes, which is not divisible by any CLS. A CLS is typically 2n in size. As a result, the remainder of the data is transferred in a small quantity, requiring I/O cycles. This type of overhead becomes significant for high bandwidth network adapters, such as those capable of transferring 10 Gbs.
Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions for transferring data from a memory to a network adapter.